DC-DC converters are widely used to supply DC power to electronic devices, such as computers, printers, and the like, and are available in a variety of configurations for deriving a regulated DC output voltage from a source of input voltage. As a non-limiting example, a buck-mode or step-down DC-DC converter generates a regulated DC output voltage whose value is less than the value of the DC source voltage. A typical step-down DC-DC converter includes one or more phases or power channels, outputs of which are combined at an output node for delivering a stepped-down DC output voltage to a load. The output stage of each power channel contains power switches, current flow paths through which are controllably switched by a pulse width modulation (PWM) signal produced by a PWM modulator, in order to switchably connect a DC source voltage to one end of an output inductor, a second end of which is connected to the output node.
In addition to regulator implementations which have no mutual coupling among the inductors, there are regulator configurations which provide mutual coupling among the output inductors. These ‘coupled-inductor’ DC-DC converters have become increasingly attractive for supplying power to portable electronic device applications, such as, but not limited to, notebook computers, and the like, which require discontinuous current mode (DCM) operation during low or relatively light load (e.g., quiescent or ‘sleep’ mode) conditions, in order to reduce power loss and preserve battery life. For DCM operation, the upper and lower MOSFETs of a respective power switching stage of the converter are turned on and off for relatively brief or ‘pulsed’ intervals, so that a conductive path for current flow through that stage's output inductor and one or the other of the respective terminals of the input power supply is provided through one or the other of a pair of power switching MOSFETs, in a discontinuous, rather than a continuous, manner, thereby reducing output current flow to accommodate the relatively light current demand during such low load conditions.
A non-limiting example of a conventional dual-phase, coupled inductor DCM buck-mode regulator or DC-DC converter, in which the output inductors of the respective phases or power channels are mutually coupled with one another, is diagrammatically illustrated in FIG. 1. As shown therein, the dual-phase DCM regulator of FIG. 1 comprises two power channels that produce respective output currents iL1 and iL2, which flow from phase nodes 115 and 215 of respective power switching stages 110 and 210 of the two phase through respective output inductors L1 and L2, that are mutually coupled with one another, such that currents induced therein due to their mutual coupling flow in the same direction (from the phase nodes into the output node OUT) as the normal currents produced by the switching of the inverter stages. These two output currents are summed at an output node OUT, to produce a composite or total output current Itotal. Output node OUT provides an output voltage Vo for powering a device LOAD, such as the microprocessor of a notebook computer, through which a load current io flows.
In order to regulate the output voltage Vo, the voltage at the output node OUT is fed back to an error amplifier (EA) 310, which is operative to compare the monitored output voltage Vo with a reference voltage VID. The voltage difference output Comp of the error amplifier 310 is supplied to a supervisory controller 315. Controller 315 is operative to precisely control the pulse widths of associated streams of pulse width modulation (PWM) waveforms, that are applied by respective PWM generators within the controller to driver circuits, whose outputs are coupled to the gates of and control the on/off switching times of the upper and lower switching devices (MOSFETs Q11/Q21 and MOSFETs Q12/Q22) of the output power switching stages 110 and 210. In a typical application, the PWM waveforms are sequenced and timed such that the interval between rising edges (or in some implementations, falling edges) thereof is constant, in order to equalize the output currents iL1 and iL2 of the two power channels.
In addition to monitoring the output voltage Vo, error amplifier 310 monitors the output currents of the two channels via respective sense resistors Rsn1 and Rsn2 that are coupled between the phase nodes 115 and 215 and a first, non-inverting (+) input 321 of a (K gain) transconductance amplifier 320. Amplifier 320 has a second, inverting (−) input 322 coupled to the output node OUT, and a sense capacitor Csns connected across its inputs. Amplifier 320 allows the sum of the current measurements to be used to precisely regulate the output resistance in a method commonly known as droop regulation or load-line regulation. The voltage output Vdroop of the amplifier 320 is coupled to a first input 331 of a subtraction circuit 330, a second input 332 of which is coupled to the output node OUT. The Vdroop voltage output of amplifier 320 is added to the output voltage Vo to provide a difference voltage Vdiff that is coupled to a first, inverting (−) input 311 of error amplifier 310. The second, non-inverting (+) input 312 of error amplifier 310 is coupled to receive the reference voltage VID. As described above, the output voltage Comp of error amplifier 310 is used by the controller 315 to control the pulse widths of the PWM waveforms that control the on/off switching of the upper and low MOSFETs of the power switching stages 110 and 210.
These PWM waveforms are shown in FIG. 2 as including a first PWM waveform PH1, that is used to control the on/off switching of the upper MOSFET switch Q11 of the power switching stage 110 of the first phase or channel, and a second PWM waveform PH2, that is used to control the on/off switching of the upper MOSFET switch Q21 of the power switching stage 210 of the second phase. For balanced-phase operation, the frequencies of the two PWM waveforms are the same and the times of occurrence of the turn-on pulses Q11-ON of the first PWM waveform PH1 are midway between the times of occurrence of the turn-on pulses Q21-ON of the second PWM waveform PH2, and vice versa. During the intervals that the pulses of the waveforms PH1 and PH2 are high, MOSFETs Q11 and Q21 are turned on thereby, so that increasing or ramping up segments iI1-1 and iL2-1 of respective currents iL1 and iL2 flow therethrough and, via phase nodes 115 and 215, through output inductors L1 and L2 to output node OUT, as shown in FIG. 2.
As further shown in FIG. 2, when the turn-on pulse Q11-ON of the PWM waveform PH1 goes low, a PWM waveform VGS—Q12, that is used to control the on/off switching of the lower MOSFET switch Q12 of the power switching stage 110 of the first phase, transitions high for a prescribed period Q12-ON, corresponding to the pulse width interval of PWM waveform VGS—Q12. With MOSFET switch Q12 turned on during this interval, the inductor current iL1 of the first channel gradually decreases or ramps down to zero from its peak value at the end of the duration or width of the turn-on pulse Q11-ON of PWM waveform PH1, as shown at iL1-2. The ramping down portion iL1-2 of the output current iL1 is supplied by a portion iS12-1 of a current iS12 that flows from ground through the source-drain path of MOSFET Q12 to phase node 115 and into the inductor L1.
In like manner, when the turn-on pulse Q21-ON of the PWM waveform PH2 goes low, a PWM waveform VGS—Q22, that is used to control the on/off switching of the lower MOSFET switch Q22 of the power switching stage 210 of the second phase, transitions high for a prescribed period Q22-ON corresponding to the pulse width interval of PWM waveform VGS—Q22. With MOSFET switch Q22 turned on during this interval, the inductor current iL2 of the second channel gradually ramps down to zero from its peak value at the end of the duration of the turn-on pulse Q21-ON of PWM waveform PH2, as shown at iL2-1. The ramping down portion iL2-2 of the output current iL1 is supplied by a portion iS22-1 of a current iS22 that flows from ground through the source-drain path of MOSFET Q22 to phase node 215 and into the inductor L2.
As pointed out above, because the output inductor L1 of the power switching stage 110 is mutually coupled with the output inductor L2 of the power switching stage 210, the current iL1 through inductor L1, that results from the successive PWM-controlled turn on of the MOSFETs Q11 and Q12, will induce a current in the inductor L2 of the second phase, shown in the current waveform iL2 of FIG. 2 as induced current iL2-3. Since the upper MOSFET Q21 of the second phase is off during this time (PH2 is low), and the polarity of its body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin to phase node 215, no current is drawn through the upper MOSFET Q21 to supply the induced current iL2-3. MOSFET Q22 of the second phase is also off at this time, since its switching PWM waveform VGS—Q22 is low. However, the polarity orientation of its body-diode allows the flow of a current iS22-2 from ground and through its body-diode as a body-diode current iD22 to phase node 215 and into inductor L2 as the induced current iL2-3.
In like manner, the current iL2 through inductor L2, that results from the successive PWM-controlled turn on of the MOSFETs Q21 and Q22, will induce a current in the inductor L1 of the first phase, shown in the current waveform iL1 of FIG. 2 as induced current iL1-3. Since the upper MOSFET Q11 of the first phase is off and the polarity of its body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin, no current is drawn through the upper MOSFET Q11 to provide the induced current iL1-3. However, even though the lower MOSFET Q12 of the first phase is off, since its switching PWM waveform VGS—Q12 is low, the polarity orientation of its body-diode is such as to allow the flow of a current iS12-2 from ground and through its body-diode as a body-diode current iD12 to phase node 115 and into inductor L1 as the induced current iL1-3.
Unfortunately, because the two induced currents iL1-3 and iL2-3 are supplied by way of respective currents iD12 and iD22 through the body diodes of lower MOSFETs Q12 and Q22, they cause significant conduction loss in these MOSFETs.